Microprocessor decoder frequency hopping spread spectrum communications receiver

ABSTRACT

The present invention is directed to a frequency hopping spread spectrum transceiver. The transceiver includes a microcontroller; a transmitter having a voltage controlled oscillator, a direct digital synthesizer, and a power amplifier; and a receiver having an amplifier, a mixer, an IF amplifier, a demodulator, and a data slicer. When transmitting, the transmitter sends a preamble that allows the receiving device to detect the signal and lock to it to receive the data. When receiving, the receiver first scans all channels and sorts them based on a Received Signal Strength Indicator (RSSI) and then attempts to lock to the channel with the strongest RSSI value by first sampling the received signal to verify the preamble, then synchronizing to the bit edges of the received signal, then detecting the start of a Start Frame Delimiter (SFD), decoding bits to verify a valid SFD and then sampling data bits to receive the data.

FIELD OF THE INVENTION

[0001] The present invention relates generally to the field of communications. More particularly, the invention relates to a frequency hopping spread spectrum technique for accepting and sorting complex waveforms to lock onto a desired remote signal.

BACKGROUND OF THE INVENTION

[0002] Fixed network communication systems may operate using wire line or radio technology. Wire line technologies include utilizing the utility distribution lines and/or telephone lines. Wireless technologies may utilize the 902-928 MHz range, which can operate without a FCC license through the use of frequency hopping spread spectrum (FHSS) transmission, which spreads the transmitted energy over the band.

[0003] According to FCC Regulations, for frequency hopping systems operating in the 902-928 MHz band, total output is as follows: 1 watt for systems employing at least 50 hopping channels; and, 0.25 watts for systems employing less than 50 hopping channels, but at least 25 hopping channels. See, 47 U.S.C. § 15.247.

[0004] FHSS systems meet the FCC specification by communicating to remote communication devices in synchronization, both in time and frequency. Using this approach, all devices know when to hop to the next channel in the sequence and what the next sequence channel is. A known FHSS system utilizes a hop rate that is faster than the data rate to send multiple sets of randomly selected frequencies in each message to distribute the transmitted energy over the communication band. This distribution is one of the FCC requirements to operate in the ISM band.

[0005] A disadvantage of the above is that it requires all devices to include a real time clock, which adds to the cost of the device. In addition, some type of battery storage system is required to maintain the real time clock in the event power should be removed from the device. Further, the requirement to step rapidly through the frequencies constrains the design of such devices and further limits cost reduction.

[0006] There have been attempts to utilize remote devices that operate asynchronously that gain synchronization with the transmitter by using a scanning receiver. One example of such a receiver is that of Harmon, U.S. Pat. No. 4,328,581. However, spurs and other unwanted signals interfere with the synchronization process in such receivers. Another problem with such systems is that the receiver is scanning channels based on a list and may be scanning channels other than the channel on which a preamble is being sent. To compensate for this, the transmitter must send the preamble for a period of time long enough to allow the receiver to scan for it and develop a bit timing. In these systems, spurs may be decoded as valid preambles, which adversely affects performance. Further, crosstalk problems may arise if weak signals from the transmitter are captured in the receiver scan sequence prior to determining the desired transmit channel.

[0007] Therefore, there is a need for a FHSS communication device that is cost efficient, meets FCC requirements for power distribution in the ISM band, and includes provisions for preventing unwanted signals from capturing the scanning receiver. The present invention is directed to these, as well as other, needs in the art.

SUMMARY OF THE INVENTION

[0008] The present invention addresses the needs identified above in that it provides for a novel method and apparatus that utilizes frequency hopping spread spectrum communications. In accordance with an aspect of the present invention, there is provided a method of validating a transmitted signal within a frequency hopping spread spectrum receiver, comprising scanning a predetermined list of channels; receiving a received signal strength indicator signal for each scanned channel; detecting a carrier signal on a selected channel; locking to the selected channel; and sampling for a start frame delimiter on the selected channel.

[0009] According to a feature of the present invention, receiving the received signal strength indicator signal further comprises converting the received signal strength indicator signal to a digital value representative of the received signal strength indicator signal, and storing the digital value in a received signal strength indicator list.

[0010] According to another feature of the invention, detecting the carrier signal further comprises searching a list of stored digital values representative of the received signal strength indicator signal for each scanned channel; determining a largest non-zero value in the list of stored digital values; setting the receiver to a first channel in accordance with the largest non-zero value; and testing a PLL lock indicator until a lock is established. A timer may be started and then sampling of a signal on the first channel is begun for a predetermined period of time to obtain a predetermined number of samples. The predetermined number of samples are correlated with ideal bit patterns to determine a number of correlation errors. If the number of correlation errors is within a predetermined tolerance, a time offset is determined based on the correlating of the predetermined number of samples with the ideal bit patterns. To verify the detection, the signal on the first channel may be resampled for the predetermined period of time to obtain a predetermined number of second samples, and the predetermined number of second samples may be correlated with the predetermined number of samples to determine a second number of correlation errors.

[0011] According to another feature, locking to the selected channel includes setting a timer; recording samples on the channel; comparing the samples to ideal preamble patterns; and correlating errors between the samples and the preamble patterns. The timer may be adjusted to a down edge of bits within the samples, and it may be determined if a number of correlation errors is within a predetermined tolerance.

[0012] According to another feature, sampling for the start frame delimiter on the selected channel includes sampling each half bit of each bit received by the receiver; voting the total number of samples to determine if each bit is a one or a zero; and comparing the bits with a predetermined start frame delimiter pattern.

[0013] According to another aspect of the present invention, an asynchronous frequency hopping spread spectrum receiver is provided. The receiver includes an integrated circuit transceiver providing a PLL lock signal and a received signal strength indicator signal and a microcontroller that receives the PLL lock signal and the received signal strength indicator signal. The microcontroller converts the received signal strength indicator signal to a digital value representative of the received signal strength indicator signal and stores the digital value in a received signal strength indicator list. The microcontroller also sets the transceiver to a channel in accordance with a largest digital value in the received signal strength indicator list and tests the PLL lock signal until a lock is established.

[0014] According to another aspect of the present invention, there is provided a method of synchronizing a frequency hopping spread spectrum receiver with a transmitter. The method includes searching a predetermined list of channels for a channel having a valid preamble; refining bit timing in order to determine center of a bit; and sampling for a start frame delimiter indicative of a beginning of a data frame on the channel.

[0015] These and other aspects of the present invention will be described in the following detailed description of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like references numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed. In the drawings:

[0017]FIG. 1 illustrates an overview of an exemplary embodiment of a frequency hopping radio in accordance with the present invention;

[0018]FIG. 2 illustrates an exemplary receive signal strength indicator (RSSI) scan process;

[0019]FIG. 3 illustrates an exemplary two scan process for ranking the RSSI;

[0020]FIG. 4 illustrates an exemplary carrier detect process;

[0021]FIG. 5 illustrates an exemplary carrier detect verification process;

[0022]FIG. 6 illustrates an exemplary carrier lock process; and

[0023]FIG. 7 illustrates an exemplary start frame delimiter and bit sampling process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Referring now to FIG. 1, there is illustrated an exemplary embodiment of a frequency hopping radio 100 in accordance with the present invention. The present invention is controlled by a microcontroller 110 and preferably implemented using a Texas Instruments TRF6900 transceiver 120, which is an integrated circuit that includes an FSK transceiver to establish a frequency-agile, half-duplex, bi-directional RF link. The chip may be used for linear (FM) or digital (FSK) modulated applications in the North American 915-MHz ISM band.

[0025] The transmitter portion of the transceiver 120 consists of an integrated voltage controlled oscillator (VCO) 122, a complete fully programmable direct digital synthesizer 124, and a power amplifier 126. The receiver portion consists of a low-noise amplifier 128, mixer 130, IF amplifier 132, limiter, FM/FSK demodulator 134 with an external LC tank circuit 136, and a data slicer 138.

[0026] The demodulator 134 may be used for analog (FM) and digital (FSK) frequency demodulation. The data slicer 138 preferably acts as a comparator. The data slicer 138 provides binary logic level signals, derived from the demodulated and low pass-filtered IF signal, that are able to drive external CMOS compatible inputs in the microcontroller 110. The noninverting input is directly connected to an internal reference voltage and the inverting input is driven by the output of the low-pass filter amplifier/post detection amplifier. The decision threshold of the data slicer 128 is determined by the internal reference voltage.

[0027] The direct digital synthesizer (DDS) 124 is based on the principle of generating a sine wave signal in the digital domain. The DDS 124 constructs an analog sine waveform using an N-bit adder counting up from 0 to 2 N in steps of the frequency register to generate a digital ramp waveform. Each number in the N-bit output register is used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog conversion, a low-pass filter is preferably used to suppress unwanted spurious responses. The analog output signal can be used as a reference input signal for a phase locked loop 140. The PLL circuit 140 then multiplies the reference frequency by a predefined factor.

[0028] The microcontroller 110 uses a three-wire unidirectional serial bus (Clock, Data, Strobe) 142 to program the transceiver 120. The internal registers contain all user programmable variables including the DDS frequency setting registers as well as all control registers. At each rising edge of the Clock signal, the logic value on the Data terminal is written into a 24-bit shift register. Setting the Strobe terminal high loads the programmed information into the selected latch.

[0029] The microcontroller 110 controls the transceiver 120 and controls the transmission and reception of data. The microcontroller 110 also controls which channel the radio 100 listens to, or transmits on, by setting registers in the DDS 124. The DDS 124 registers, in turn, control the phase locked loop 140 and the VCO 122 to set the transmit and receive frequencies. Those skilled in the art will recognize that this is one of several possible methods for setting the transmit and receive frequencies.

[0030] In transmit mode, the transceiver 120 has a transmit output power of 0 dBm. An external Power Amplifier (PA) 144 provides an additional 24 dB of gain, resulting in a total output power of +24 dBm. The microcontroller 110 drives a Transmit/Receiver switch 146, which advantageously allows one antenna to be used for both the transmitter and receiver portions of the transceiver 120.

[0031] In receive mode, an external low noise amplifier (LNA) 148 and the internal LNA 128 are used to amplify the received signal. The received signal is “mixed down” by the mixer 123 for processing and then amplified. The signal strength indicator 152 is an output and is monitored by the microcontroller 110. The receiver then converts from a frequency-modulated signal to baseband signal using the demodulator 134 and the data slicer 138. The microcontroller 110 is responsible for decoding the raw baseband signal, synchronizing to bit edges.

[0032] As will be described in greater detail below, in receive mode, the microcontroller 110 uses the Serial Interface 142 to set the receive frequency and then looks for a valid preamble from a remote transmitting device. The process of looking for a valid preamble involves first scanning all 25 channels looking for single strength on one or more of the 25 channels. After scanning the channels and sorting the possible preamble channels based on RSSI, the receiver attempts to detect a valid preamble on the channel with the strongest RSSI. If a valid preamble is not detected, the microcontroller 110 uses the Serial Interface 142 to change the frequency to the channel with the next highest RSSI value. If no preamble is detected, the microcontroller “hops” channels every 1 ms. Other hop timing may be used. When a valid preamble is detected, the receiving device can synchronize with the transmitter to receive a packet of information, as detailed below. Synchronization involves hopping in synch with the transmitter to additional preamble and data channels.

[0033] A Lock Detect signal 150 from the transceiver 120 indicates that the radio 100 is locked on the desired receive frequency. After writing the Serial Interface 142, which instructs the radio 100 to change the receiver channel, the microcontroller 110 waits for Lock Detect 150 to be asserted, signaling the receive channel can be monitored for a stable received signal. This settling time, in addition to the time required to write the registers via the Serial Interface 142, determines the per channel scan time (e.g., 1 ms).

[0034] An exemplary embodiment implemented using the radio 100 will now be explained. The present invention does not require a separate clock or other synchronization information, nor does it require an indication of a valid signal from the transceiver 120 to decode the incoming signal. The microcontroller 110 performs the tasks of decoding and validating the signals, where each signal preferably contains a preamble, start frame delimiter (SFD) and a data frame. The SFD indicates that the preamble has ended and that the data frame will follow. In accordance with the present invention, the SFD must appear within a predetermined maximum time after the start of the preamble in order for a signal to be considered valid. Following receipt of a valid SFD, the microcontroller 110 maintains bit timing and records the data bits.

[0035] Referring now to FIG. 2, a Received Signal Strength Indictor Scan process of the overall decoding process of the present invention will now be described. The decoding process involves sampling the incoming signal rapidly and correlating a set of samples with a known pattern to determine if a preamble is present. In accordance with the present invention, the preamble preferably begins with a zero and ends with a one.

[0036] The process begins by setting a counter (x) to zero, then at step 200, a timer in the microcontroller 110 is started and a channel is selected. The channel is selected sequentially from a list of channels (e.g., 25 channels) to be scanned. At step 202, the microcontroller 110 tests the PLL lock detect indicator 150 at intervals equal to a bit time (e.g., 56.48 μs) until a lock is established. Once a lock is established at step 202, the timer is set at step 204 to allow the receiver to settle for a configurable settling time, where the present invention uses an RSSI settling time of 200 μs. At step 206, the Receive Signal Strength Indicator (RSSI) 152 is monitored by the microcontroller 110 using an analog-to-digital converter within the microcontroller 110. The microcontroller 110 stores the results of the converted RSSI indicator 152 in a list that corresponds to the channel list noted above by position and length. At step 207, a channel counter value (x) is incremented by one and then tested to see if it is greater than or equal to 25. If x is less than 25, processing returns to step 200 to sample the next channel. If the counter is equal to or greater than 25, then processing exits to search the list (see, FIG. 3) that was created through the process of FIG. 2.

[0037] Referring now to FIG. 3, there is illustrated the carrier detect portion of the decoding process of the present invention. At step 208, the RSSI list created at step 206 is searched for the largest value that is greater than a configurable RSSI threshold. This value corresponds to the strongest signal, as noted above. If a non-zero value is not found, then the RSSI scan process of FIG. 2 is repeated. At step 210, the largest non-zero value determined is replaced with a zero. Next, at step 212, the offset into the RSSI list of the signal determined at step 208 to have the largest non-zero value is calculated and used to select a channel value at the same offset into the channel list. The transceiver 120 is then set to receive on this channel. For example, if the signal determined in step 208 is the ninth channel in the RSSI list, the transceiver will be set to the ninth channel on the channel list. At step 214, the PLL lock 150 is tested at intervals equal to the bit time (56.48 μs) until the lock is established.

[0038] At step 216, a timer in the microcontroller 110 is set to trigger at a time equal to II bit times (e.g., 11*56.48 μs). At step 218, the signal on the channel determined in step 212 is sampled for two preamble bit times (e.g., 2*56.48 μs). In accordance with the present invention, 32 samples over the two preamble bit times are recorded. Alternatively, sub-samples may be recorded between samples and used to form samples by simple voting if processor speed allows.

[0039] At step 220, the samples are analyzed as two 16 sample halves. Each half is compared with 16 ideal patterns. In accordance with the present invention, the ideal patterns are generated from the 16 rotations of 0xF00F. At step 222, correlation is performed by performing an XOR (exclusive OR) operation on the four bytes of the samples with each of the four bytes of the ideal pattern. The number of bit positions in which the samples and pattern differ (Hamming distance) is the number of correlation errors for that pattern. The number of ones in the XOR result is the number of errors and is preferably calculated using the sum of four lookups in a 256-byte table containing the number of ones in each index byte. The number of rotations needed to achieve the pattern with the fewest errors is stored by the microcontroller 110. If the number of correlation errors is within a configurable tolerance, the signal is considered to be a preamble candidate. The present invention uses a default tolerance of 3 bit errors. If the number of correlation errors is greater than the tolerance, the carrier detect process of FIG. 3 is repeated, using the channel with the next highest RSSI value. If this next highest RSSI value does not exceed the RSSI threshold, the process restarts at FIG. 2.

[0040] At step 224, the value of a free running timer set at step 216 is used to compute a time offset to the next occurrence of the identical pattern in accordance with the number of pattern matching rotations stored at step 222. The pattern is matched to one of a list of patterns and the time adjustment is performed such that the carrier detect verification (i.e., repeating the 32 samples looking for valid preamble) is now aligned with the pattern that was found on the first attempt. In other words, the timer is adjusted so that an ideal carrier detect verification matches the pattern from the first carrier detect.

[0041]FIG. 4 illustrates a carrier detect verify process, which occurs over two bit times of sampling. At step 226, when the timer set at step 216 (FIG. 3) expires, another timer in the microcontroller is set to expire in six bit times (6*56.48 μs). At step 228, the signal on the transceiver channel set at step 212 is sampled for two bit times (2*56.48 μis). 32 samples over the two preamble bit times are recorded by the microcontroller 110. As described above, sub-samples may be recorded between samples and used to form samples by simple voting if processor speed allows.

[0042] Also at step 230, the 32 samples are analyzed as two 16 sample halves and compared to the pattern recorded at step 222 (FIG. 3). The sample must contain less than the number of configurable correlation errors plus two. If the errors in the sample are found to exceed the limit, the carrier detect process of FIG. 3 is repeated using the channel with the next highest RSSI value. If this next highest RSSI value does not exceed the RSSI threshold, the process restarts at FIG. 2.

[0043] At step 232, the free running timer set at step 226 is adjusted to expire in order to center the sampling period in a carrier lock process (described below with reference to FIG. 5) across a down edge of a preamble bit. The free running timer is adjusted in accordance with a value computed using the number of pattern rotations stored at step 222.

[0044] Referring now to FIG. 5, there is illustrated the carrier lock process of the present invention. At step 234, a timer is set to expire after a time period equal to seven bit times (7*56.48 μs). At step 236, 16 samples over one-half of a preamble bit time beginning one-quarter of a bit time prior to the previously inferred location of the down edge are recorded. The location was inferred through the carrier detect and carrier detect verify processes, described above.

[0045] At step 238, the 16 samples are correlated with 15 ideal preamble patterns and 15 inverted ideal preamble patterns, which are stored in a table. The table is preferably organized to represent inverted preamble patterns at one end of the table and preamble patterns at the other end. The patterns are in a sequence that represents the desired pattern shifted to the left and then right by one bit, two bits, etc. In each successive carrier lock, the starting point in the table is adjusted in order to refine the timing to avoid failure. A pattern match in the inverted portion of the table indicates the beginning of the SFD.

[0046] At step 240, if the number of correlation errors is within the predetermined tolerance for the preamble correlation pattern, the signal is considered to be a preamble candidate by the microcontroller 110. The timer set at step 234 is adjusted to center on the next down edge and the process repeats.

[0047] If at step 240 the number of correlation errors is within the predetermined tolerance for the SFD correlation pattern, the SFD has started. Bit sampling is performed to find the rest of the SFD pattern as described below with reference to FIG. 6. The tolerances for carrier lock is preferably the same in both cases, regardless of whether a preamble bit or a SFD bit is being detected. The tolerance is configurable, but the present invention uses a default of 3 bit errors.

[0048] If a total of two carrier lock preamble correlation attempts fail or the total preamble time before the SFD is exceeded, the signal is no longer considered a preamble candidate and the decoding process returns to perform the RSSI scan of FIG. 2.

[0049] Referring now to FIG. 6, there is illustrated the SFD and bit sampling process of the present invention. At step 242 a bit-center timer is started to trigger in the middle of each half-bit. Herein, a bit is a Manchester encoded bit made up of two half bits of one-half bit time. Manchester Encoding is well known in the art an encodes a logic 0 by indicated by a 0 to 1 transition at the center of a bit and a logic 1 by indicating a 1 to 0 transition at the center of a bit.

[0050] At step 244, the half-bit is sampled as many times a possible in accordance with processor speed. It is preferable to begin sampling one-half of a sample period prior to the half-bit center.

[0051] At step 246, equal numbers of samples from each half of the Manchester bit are voted by bit-wise first inverting the first samples and then counting the number of samples of the 16 that are ones. If fewer than half are ones, the Manchester bit is considered a zero data bit. If half or more are ones, then the Manchester bit is considered to be a one data bit.

[0052] In accordance with the present invention, the SFD is composed of 32 Manchester one bits followed by the following Manchester bits: 0000 1100 1011 1101 (left bit first). Other sequences of bits may be used. No bit errors are tolerated in the SFD. If the SFD is not found, then the RSSI scan of FIG. 2 is repeated.

[0053] After the SFD found, the transceiver 120 is in synchronization with the transmitter, and continues to sample the bits to receive the data transmitted by the transmitter.

[0054] Referring now to FIG. 7, in accordance with an aspect of the present invention, a two-step RSSI scan process may be implemented to determine which of the channels is the appropriate data channel. At step 300, the first scan is performed wherein the receiver scans the complete list of channels, quantifies the RSSI indicator 152 and sorts the list for the strongest RSSI levels. A subset of the strongest channels (e.g., 3 channels) may be developed from this first scan of the channels. The subset of channels may consist of more or less channels than three.

[0055] At step 302, the first scan is repeated a predetermined number of times, e.g., four times, where a subset of strongest channels is developed for each scan. The scan may be repeated an alternate number of times. At the completion of the final RSSI first scan, the strongest channels from all of the scans are sorted by RSSI level.

[0056] At step 304, a second scan is performed wherein a scan is performed of the highest RSSI level, as determined by the first scan process above. At step 306, the strongest signal is analyzed for preamble and a start frame delimiter (SFD) bit patterns that will further qualify the channel as the transmit channel. The process of determining if the SFD bit patterns are present in a particular channel has been described in the preceding paragraphs. If the preamble bit patterns are not present, then the second strongest channel and so on is analyzed for valid preamble and SFD bit patterns until found. If the preamble bit pattern is not found during the second scan process, the first scan process is repeated.

[0057] Various modifications of the invention, in addition to those described herein, will be apparent to those of skill in the art in view of the foregoing description. Such modifications are also intended to fall within the scope of the appended claims. For example, a bit time other than 56.48 μs may be used. In addition, bits may be encoded using an encoding scheme other than Manchester Encoding. 

What is claimed:
 1. In a frequency hopping spread spectrum receiver, a method of validating a transmitted signal, comprising: scanning a predetermined list of channels; checking a received signal strength indicator signal for each scanned channel; detecting a carrier signal on a selected channel; locking to said selected channel; and sampling for a start frame delimiter on said selected channel.
 2. The method of claim 1, wherein said receiving said received signal strength indicator signal further comprises: converting said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal; and storing said digital value in a received signal strength indicator list.
 3. The method of claim 1, wherein said detecting said carrier signal further comprises: searching a list of stored digital values representative of the received signal strength indicator signal for each scanned channel; determining a largest non-zero value in said list of stored digital values; setting said receiver to a first channel in accordance with said largest non-zero value; and testing a PLL lock indicator until a lock is established.
 4. The method as recited in claim 3, further comprising: starting a timer; sampling a signal on said first channel for a predetermined period of time to obtain a predetermined number of samples; and correlating said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.
 5. The method as recited in claim 4, further comprising: determining if said number of correlation errors is within a predetermined tolerance; and determining a time offset based on said correlating of said predetermined number of samples with said ideal bit patterns.
 6. The method as recited in claim 4, wherein said predetermined period of time is 2 bit times and wherein said predetermined number of samples is
 32. 7. The method as recited in claim 4, wherein said correlating said predetermined number of samples with said ideal bit patterns comprises: dividing said predetermined number of samples into two sets; performing an exclusive OR operation on said two sets with said ideal bit patterns; determining a number of ones as a result of the exclusive OR operation, said number of ones being indicative of a number of errors; and determining the number of rotations needed to achieve the ideal bit pattern with the fewest errors, said of said rotations being generated by rotating 0xF00F.
 8. The method as recited in claim 4, further comprising: resampling said signal on said first channel for said predetermined period of time to obtain a predetermined number of second samples; and correlating said predetermined number of second samples with said predetermined number of samples to determine a second number of correlation errors.
 9. The method as recited in claim 1, wherein said locking to said selected channel comprises: setting a timer; recording samples on said channel; comparing said samples to ideal preamble patterns; and correlating errors between said samples and said preamble patterns.
 10. The method as recited in claim 9, further comprising: adjusting said timer to a down edge of bits within said samples; and determining if a number of correlation errors is within a predetermined tolerance.
 11. The method as recited in claim 1, wherein said sampling for said start frame delimiter on said selected channel comprises: sampling each half bit of each bit received by the receiver; voting the total number of samples to determine if each bit is a one or a zero; and comparing the bits with a predetermined start frame delimiter pattern.
 12. The method as recited in claim 11, wherein each bit is Manchester Encoded.
 13. An asynchronous frequency hopping spread spectrum receiver, comprising: an integrated circuit transceiver providing a PLL lock signal and a received signal strength indicator signal; and a microcontroller that receives said PLL lock signal and said received signal strength indicator signal, wherein said microcontroller converts said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal and stores said digital value in a received signal strength indicator list, and wherein said microcontroller sets said transceiver to a channel in accordance with a largest digital value in said received signal strength indicator list and tests said PLL lock signal until a lock is established.
 14. The receiver of claim 13, wherein said microcontroller samples a signal on said channel for a predetermined period of time to obtain a predetermined number of samples and correlates said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.
 15. The receiver as recited in claim 14, wherein said microcontroller determines if said number of correlation errors is within a predetermined tolerance; and determines a time offset based on said correlating of said second predetermined number of samples with said ideal bit patterns.
 16. The receiver as recited in claim 14, wherein said microcontroller resamples said signal on said channel for said predetermined period of time to obtain a predetermined number of second samples and correlates said predetermined number of second samples with said predetermined number of samples to determine a second number of correlation errors.
 17. The receiver as recited in claim 13, wherein said microcontroller locks to said selected channel by recording samples on said channel and correlating errors between said samples and preamble patterns.
 18. The receiver as recited in claim 13, wherein said microcontroller samples said channel for a start frame delimiter by sampling each half bit of each bit received by the receiver and voting the total number of samples to determine if each bit is a one or a zero, and then comparing the bits with a predetermined start frame delimiter pattern.
 19. A method of synchronizing a frequency hopping spread spectrum receiver with a transmitter, comprising: searching a predetermined list of channels for a channel having a valid preamble; refining bit timing in order to determine center of a bit; and sampling for a start frame delimiter indicative of a beginning of a data frame on said channel.
 20. The method as recited in claim 19, wherein searching said predetermined list of channels comprises: receiving a received signal strength indicator signal for each scanned channel; converting said received signal strength indicator signal to a digital value representative of said received signal strength indicator signal; and storing said digital value in a received signal strength indicator list.
 21. The method of claim 20, further comprising: determining a largest non-zero value in said list of stored digital values; setting said receiver to a first channel in accordance with said largest non-zero value; and testing a PLL lock indicator until a lock is established; sampling a signal on said first channel for a predetermined period of time to obtain a predetermined number of samples; and correlating said predetermined number of samples with ideal bit patterns to determine a number of correlation errors.
 22. The method as recited in claim 21, further comprising: determining if said number of correlation errors is within a predetermined tolerance; and determining a time offset based on said correlating of said predetermined number of samples with said ideal bit patterns.
 23. The method as recited in claim 19, wherein said refining bit timing in order to determine center of a bit comprises: recording samples on said channel; comparing said samples to ideal preamble patterns; correlating errors between said samples and said preamble patterns; adjusting a timer to a down edge of bits within said samples; and determining if a number of correlation errors is within a predetermined tolerance.
 24. The method as recited in claim 19, wherein said sampling for said start frame delimiter on said channel comprises: sampling each half bit of each bit received by the receiver; voting the total number of samples to determine if each bit is a one or a zero; and comparing the bits with a predetermined start frame delimiter pattern. 